As semiconductor device sizes continue to get smaller, nanowires are becoming a more attractive alternative for interconnecting various device components in relatively small circuits. In addition to their relatively small dimensions, nanowires may exhibit certain properties not found in the same material in bulk form, which may also be advantageous in certain configurations.
One example device which incorporates nanowires is set forth in U.S. Pat. Pub. No. 2013/0270512 to Radosavljevic et al. This reference discloses architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). Multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. Individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers.
Despite the existence of such configurations, further enhancements in semiconductor devices incorporating nanowires may be desirable in some applications, such as next generation devices with relatively small dimensions.